When data are received via serial communication channels, bit errors always arise to a greater or lesser extent in practice under real reception conditions. That is to say that the original values of the data cannot be recovered by the receiver without error.
The resulting bit error rate is typically at its lowest when the receiver samples the data at a recovered clock rate that corresponds to the transmitter clock rate, that is to say at the time at which the receiver clock is synchronized to the clock rate of the data that are being sent via the channel. As the transmission length without resynchronization between the transmitter clock rate and the receiver clock rate increases, the average bit error rate increases.
In the case of an existing DigRF interface, the attainment of a low bit error rate has to date been based on oversampling of the data signal on up to six sampling phases. Oversampling means that the data signal is sampled at a plurality of sampling times over a bit period duration T of the data signal. That is to say that, in the case of 6-fold oversampling, the data signal is sampled at six successive times within one bit period.
If the influences of phase noise are ignored, the sampling times within a bit period are at evenly distributed intervals of time from one another. In the case of six sampling phases used, this interval of time corresponds to a phase offset of
  T  6or 60°, and in the case of four sampling phases used it corresponds to
  T  4or 90°.
In a MIPI® DigRF interface (Mobile Industry Processor Interface), data are transmitted in layer 1 by means of data frames, the frames comprising a synchronization sequence which is always the same, a frame header—which determines the length of the frame, inter alia—and the resulting and subsequent user data (payload).
The invariable synchronization sequence at the start of a frame therefore makes it possible to check which sampling phases can be taken as a basis for detecting the data from the synchronization sequence which are consequently known at the receiver end. From these sampling phases, the one that is as central as possible within the bit period duration T is selected. Normally, this also corresponds to that sampling phase for which the sampling time involves the voltage difference between the two differential transmission signals—which represent the data—being at its greatest and hence the possibility of misinterpretation of the differential signal being at its lowest. In this case, DigRF systems especially use the concept of differential signaling (Low Voltage Differential Signaling). This involves a logic “1” being represented by a positive voltage difference between the voltages applied to the two transmission signals, and a logic “0” accordingly being represented by a negative voltage difference.
During the continued transmission of the frame, no further error correction takes place at the level of layer 1 that goes beyond the above selection of the reference sampling phase. Hence, a worsening data signal sometimes cannot be identified. In this case, the worsening of the data signal may involve a multiplicity of effects, such as increasing phase offset, relatively high phase noise, also called jitter, for the individual sampling times or a decreasing aperture angle in the eye diagram of the data signal.
Consequently, errors at the receiver end can be corrected only by means of redundant error correction codes, such as Reed-Solomon codes, at a relatively high protocol level or by re-requesting the defective frame—likewise at a relatively high protocol level.
Furthermore, the reference sampling phase as ascertained above is not always found to be the best possible sampling phase in practice, depending on the various cited impairments of the data signal.